The present invention relates to a semiconductor device.
A phase locked loop (to be referred to as a PLL hereinafter) circuit can obtain a frequency signal having a desired frequency with high accuracy by detecting a phase difference between a reference signal as a reference and an output frequency signal from a voltage controlled oscillator by using a phase frequency detector.
In a locked state in which the output frequency of the frequency signal is stable, the reference signal and frequency signal are in phase with each other, and the output from the phase frequency detector is ideally zero.
A generally used phase frequency detector, however, has a configuration in which a flip-flop for receiving the reference signal and a flip-flop for receiving the frequency signal are reset on the basis of the outputs from these two flip-flops. Even in the locked state, therefore, the phase frequency detector actually generates an output signal.
A charge pump circuit connected to the output of the phase frequency detector converts the signal generated by the phase frequency detector in this locked state into an electric current, thereby generating a control voltage containing a periodic fluctuation component. The voltage controlled oscillator converts the frequency of this control voltage to generate a spur in the output frequency.
A reference disclosing the conventional PLL circuit is as follows.
Japanese Patent Laid-Open No. 2001-119297